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CMX644A v.22 and bell 212a modem ? 2000 consumer microcircuits limited d/644a/6 june 2000 provisional issue features applications v . 22/bell 212a compatible modem telephone telemetry systems inte grated dtmf encoder remote utility meter reading call progress/accurate answer tone detection security systems/cash terminals line reversal a nd ringing detector industrial control systems low power operation (2.7v) pay - phones fully integrated uart functions cable tv set - top boxes 1.1 brief description the CMX644A v . 22 modem is intended for use in any telephone based information and telemetry system with low power requirements. using v . 22 signalling, fast call set up times and robust error resistant transmission can be implemented by efficient low power circuits. the circuit can operate at 1200b/s full duplex over 2 - or 4 - wire circuits. control of the device is via a simple high speed serial bus and data m ay be optionally formatted by the on - chip uart. this allows easy interfacing to a host controller. the data transmitted and received by the modem is also transferred over the same high speed serial bus. in addition to v . 22, support is included to meet t he bell 212a standard. the integrated dtmf encoder can be used as part of the dial out function. all 16 dtmf combinations are available along with a single tone ?melody? mode. the answer tone generator/detector and call progress tone detectors included o n the CMX644A make the set - up of a telephone call a simple matter for the host controller. in many data collection and telemetry systems low power consumption is important. the CMX644A features a ?zero power? standby mode. whilst in standby, the device c an still detect a ringing voltage or line voltage reversal. the CMX644A can operate on a supply voltage between 3.0v and 5.5v across the full temperature range of - 40c to +85c. a low impedance pull down output is provided for a hook relay. the CMX644A is pin compatible with the cmx624 v23/bell 202 modem also from cml.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 2 d/644a/6 contents section page 1.1 brief description ................................ ................................ .................. 1 1.2 block diagram ................................ ................................ ...................... 3 1.3 signal list ................................ ................................ ............................ 4 1.4 external components ................................ ................................ .......... 6 1.5 general description ................................ ................................ ............. 7 1.5.1 ?c - bus? interface ................................ ................................ ..... 7 1.5.2 uart ................................ ................................ ....................... 8 1.5.3 software description ................................ ............................. 10 1.6 application notes ................................ ................................ .............. 21 1.6.1 line interface ................................ ................................ ......... 21 1.6.2 ring detector interface ................................ ......................... 23 1.6.3 software protocol for transmitting psk data by tes ........... 24 1.6.4 software protocol for receiving psk data bytes ............... 25 1.6.5 handling underflow and overflow conditions .................... 25 1.7 performance specification ................................ ................................ 27 1.7.1 electrical performance ................................ .......................... 27 1.7.2 packaging ................................ ................................ .............. 32
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 3 d/644a/6 1.2 block diagram figure 1 block diagram
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 4 d/644a/6 1.3 signal list CMX644A d2/d5/p4 signal description pin no. name type 1 xtaln o/p the inverted output of the on - chip oscillator. 2 xtal/clock i/p the input to the on - chip oscillator, for external xtal circuit or clock. 3 serial clock i/p the ?c - bus? s erial clock input. this clock, produced by the m controller, is used for the transfer timing of commands to and from the device. 4 command data i/p the ?c - bus? serial data input from the m controller. data is loaded into this device in 8 - bit bytes, msb ( b7) first, and lsb (b0) last, synchronised to the serial clock. 5 reply data t/s the ?c - bus? serial data output to the m controller. the transmission of reply data bytes is synchronised to the serial clock under control of the csn input. this 3 - state ou tput is held at high impedance when not sending data to the m controller. 6 csn i/p the ?c - bus? data loading control function: this input is provided by the m controller. data transfer sequences are initiated, completed or aborted by the csn signal. 7 i rqn o/p this output indicates an interrupt condition to the m controller by going to a logic ?0?. this is a ?wire - orable? output, enabling the connection of up to 8 peripherals to 1 interrupt port on the m controller. this pin has a low impedance pulldown to logic ?0? when active and a high impedance when inactive. an external pull - up resistor is required. 8 top o/p the output of the transmit gain control. 9 txo o/p the output of the line driver amplifier. 10 txn i/p the inverting input to the line driver amplifier. 11 txon o/p the inverted output of the line driving amplifier. pins txo and txon provide symmetrical outputs for use with a balanced load to give sufficient tx line signal levels even at low v dd .
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 5 d/644a/6 1.3 signal list (continued) CMX644A d2/d5/p4 signal description pin no. name type 12 v ss p ower the negative supply rail (ground). 13 v bias o/p a bias line for the internally circuitry, held at ? v dd . this pin must be decoupled by a capacitor mounted close to the device pins. 14 rlyd rv o/p an open - drain output for controlling a relay. 15 rxp i/p the non - inverting input of the receive op - amp. 16 rxn i/p the inverting input of the receive op - amp. 17 rxo o/p the output of the receive op - amp. 18 rt bi open - drain output and sch mitt trigger input forming part of the ring or line polarity reversal detector. an external resistor to v dd and a capacitor to v ss should be connected to rt to filter and extend the rd input signal. 19 rd i/p input to the ring or line polarity reversal detector. 20, 21, 22 - n/c no connections should be made to these pins. 23 atodcap o/p the reference voltage for the internal a to d of the receiver. this pin must be decoupled by a capacitor mounted close to the device pins. 24 v dd p ower the posit ive supply rail. levels and thresholds within the device are proportional to this voltage. should be decoupled to v ss by a capacitor mounted close to the device pins. notes: i/p = input o/p = output n/c = no (external) connections b/i = bi directional t/s = tristate this device is capable of detecting and decoding small amplitude signals. it is recommended that the printed circuit board is laid out with a ground plane in the CMX644A area to provide a low impedance connection between the v ss pin and the v dd and v bias decoupling capacitors. the receive path should be protected as much as possible from extraneous signals.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 6 d/644a/6 1.4 external components r1 100k w * c1, c2 1 8pf x1 3.6864mhz, 7.372800mhz or 11.0592mhz c3, c4 c5 0.1 m f 1 m f resistors 1%, capacitors 20% unless otherwise stated. * r1 should be selected so that t he irqn pin has returned to its normal (high) state before the csn pin goes high. figure 2 recommended external components for typical application notes on xtal osc and clock dividers frequency and timing accuracy of the CMX644A is determined by the clock present at the xtal/clock pin. this may be generated by the on - chip oscillator inverter using the external components c1, c2 and x1 of figure 2, or may be supplied from an external source to the xtal/clock input. if the clock is supplied from an external source, c1, c2 and x1 should not be fitted. the on - chip oscillator is turned off in the 'zero - power' mode. if the clock is provided by an external source which is not always running, then the 'zero - power' mode must be set when the clock is not available. failure to observe this rule may cause a rise in the supply current drawn by CMX644A.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 7 d/644a/6 1.5 general description 1.5.1 ?c - bus? interface this block prov ides for the transfer of data and control or status information between the CMX644A?s internal registers and the c over the ?c - bus? serial bus. each transaction, see figure 3, consists of a single register address byte sent from the c which may be follow ed by a single data byte sent from the c to be written into one of the CMX644A?s write only registers, or a single byte of data read out from one of the CMX644A?s read only registers. data sent from the c on the command data line is clocked into the cmx 644a on the rising edge of the serial clock input. reply data sent from the CMX644A to the c is valid when the serial clock is high. the interface is compatible with the most common c serial interfaces such as sci, spi and microwire, and may also be eas ily implemented with general purpose c i/o pins controlled by a simple software routine. see section 1.7.1 and figure 9 for detailed ?c - bus? timing requirements. figure 3 ?c - bus? transactions
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 8 d/644a/6 1.5.2 uart this block connects the c, via the ?c - bus? interface, to the received data from the psk demodulator and to the transmit data input to the psk modulator. as part of this function, the block can be programmed to convert data to be transmitted from 7 or 8 - bit bytes to asynchronous data characters, adding start and stop bits and - optionally - a parity bit to the data before passing it to the psk modulator. similarly, in the receive direction it can extract data bits from asynchronous characters coming from the psk demodulator, stripping off the start and stop bits and performing an optional parity check on the received data before passing the result over the ?c - bus? to the c. bits 0 - 5 of the uart mode register control the number of stop and data bits and the p arity options for both receive and transmit directions. data to be transmitted should be loaded by the c into the tx data byte register when the tx data ready bit (bit 1) of the flags register goes high. it will then be treated by the tx uart block in on e of two ways, depending on the setting of bit 5 of the uart mode register: if bit 5 of the uart mode register is ?0? (?sync? mode) then the 8 bits from the tx data byte register will be transmitted sequentially lsb (d0) first. if bit 5 of the uart mode register is ?1? (?async? mode) then the 7 or 8 bits will be transmitted as asynchronous data characters according to the following format: one start bit (space). 7 or 8 data bits from the tx data byte register (d0 - d6 or d0 - d7) as determined by bit 0 of the uart mode register. lsb (d0) transmitted first. optional parity bit (even or odd parity) as determined by bits 1 and 2 of the uart mode register. zero, one or two stop bits (mark) as determined by bits 3 and 4 of the uart mode register. in both case s data will only be transmitted if bit 6 of the tx psk mode register is set to ?1?. failure to load the tx data byte register with a new value when required will result in bit 2 (tx data underflow) of the flags register being set to ?1? and a continuous mark (?1?) signal will then be transmitted until a new value is loaded into tx data byte register. figure 4a transmit uart function (async)
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 9 d/644a/6 received data from the psk demodulator goes into the receive part of the uart block, where it is handled in o ne of two ways depending on the setting of bit 5 of the uart mode register: if bit 5 of the uart mode register is ?0? (?sync? mode) then the receive part of the uart block will simply take 8 consecutive bits from the demodulator and transfer them to the r x data byte register (the first bit going into the d0 position). if bit 5 of the uart mode register is ?1? (?async? mode) then the received data output of the psk demodulator is treated as asynchronous characters each comprising: a start bit (space). 7 or 8 data bits as determined by bit 0 of the uart mode register. these bits will be placed into the rx data byte register with the first bit received going into the d0 position. an optional parity bit as determined by bits 1 and 2 of the uart mode regist er. if parity is enabled (bit 2 of the uart mode register = ?1?) then bit 7 of the flags register will be set to ?1? if the received parity is incorrect. any number of stop bits (mark). bit 3 (rx data ready) of the flags register will be set to ?1? ever y time a new received value is loaded into the rx data byte register. if the previous contents of the rx data byte register had not been read out over the ?c - bus? before the new value is loaded from the uart then bit 4 (rx data overflow) of the flags regis ter will also be set to ?1?. figure 4b receive uart function (async) the c - bus serial clock should be fast enough to ensure that an rx data ready interrupt is serviced completely within a time which is less than 8 bit - times at 1200 baud, i.e. in l ess than 6.67ms.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 10 d/644a/6 1.5.3 software description write - only ?c - bus? registers register name hex address/ command bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d 0) general reset $01 n/a n/a n/a n/a n/a n/a n/a n/a set - up $e0 0 relay drive detect det1 detect det0 loop - back: l1 loop - back: l0 xtal frq: x1 xtal frq: x0 tx tones $e1 tone sel tone / notone dtmf / modem tones dtmf / sngl d3 d2 d1 d0 gain blocks $e2 txgain tg3 txgain tg2 txgain tg1 txgain tg0 rxgain rg3 rxgain rg2 rxgain rg1 rxgain rg0 tx data byte $e3 d7 d6 d5 d4 d3 d2 d1 d0 uart mode $e4 0 0 sync/ async stop bits b stop bits a parity enable parity odd/ even dat a bits 8/7 tx psk mode $e7 0 txon enab scramb unlock scramb enable equal et1 equal et0 enable hi / lo band rx psk mode $e8 0 cpbw select de - scramb unlock de - scramb enable equal er1 equal er0 enable hi / lo band irq mask bits $ee rx parity ring detect detect rx data over - flow rx data ready tx data under - flow tx data ready un - scram mark write - only register descriptions general reset ($01) the reset command has no data attached to it. application of the general reset sets all write - only regi ster bits to ?0?. set - up register ($e0) (bit 7) reserved for future use. this bit should be set to ?0?. relay drive (bit 6) this bit controls a low impedance pull - down transistor connected to the rlydrv pin to assist with the operation of an ?off - hook relay?. when set to ?1? the transistor acts as a pull - down and will sink current. when set to ?0? the pin is in a high impedance state. detect det1 and det0 (bits 5 and 4) these 2 bits control the operation of the receiver filter in order to facilitate the detection of the following signals as shown in the table below: det1 bit 5 det0 bit 4 required rx hi/lo band setting (register $e8, bit 0) detection mode 0 0 as required for rx psk psk carrier 0 1 lo = ?0? call progress 1 0 hi = ?1? answer tone 1 1 as required for rx psk detectors off rx psk mode register enable bit should be set to ?1? for answertone and call progress detection.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 11 d/644a/6 loopback l1 and l0 (bits 3 and 2) these 2 bits control internal signal paths such that loopback tests can be performed. function is according to the following table: l1 bit 3 l0 bit 2 0 0 normal device operation: no loopback. 0 1 local analogue loopback: the output of the tx gain block is routed to the input of the receiver gai n block. (the connection between the receiver op - amp and gain block is broken). 1 0 local digital loopback: data is loaded into the tx data byte register in the usual way via the ?c - bus? when indicated by the tx data ready flag. this digital data is i nternally retimed serially to the modem bit - rate and is then clocked into the receiver buffer. when the receiver buffer is full the rx data ready flag will be set and the data can then be read out of rx data byte register via the ?c - bus?. 1 1 reserved f or future use. xtal frq x1 and x0 (bits 1 and 0) these two bits control the internal primary clock dividers to allow for a choice of 3 crystal frequencies. they can also be set to put the device into ?zero power? mode: in this mode all functions are p owersaved, except for the ?c - bus? and the ring detector. in ?zero power? the crystal oscillator is disabled and the bias resistor chain is disconnected from the supplies. note: when the device is brought out of ?zero power? mode, the software should a llow at least 20ms for the crystal oscillator to re - start and for the bias capacitor to re - charge, before proceeding with any further device functions. the function is given by the following table: x1 bit 1 x0 bit 0 crystal / mode 0 0 ?zero power? 0 1 3.6864mhz crystal 1 0 7.3728mhz crystal 1 1 11.0592mhz crystal
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 12 d/644a/6 tx tones register ($e1) this register is used to transmit both dtmf and modem progress tones. tonesel (bit 7) this bit selects the ?answer tone? frequency in the receive detector . a ?0? selects 2225hz and a ?1? selects 2100hz. tone/notone (bit 6) this bit should be used to begin and end the transmission of tones once the required frequency has been programmed. when set to ?1? the tone will be transmitted; when set to ?0? a notone (bias voltage) will be generated. dtmf/modem tones (bit 5) when this bit is set to ?1? the device is configured for dtmf. when it is set to ?0? the device is configured to transmit modem progress tones. dtmf/sngl (bit 4) for normal dtmf operation this bit should be set to ?0?. for test purposes it can be set to ?1? in order to select the tone frequencies individually. the following table shows the settings required for transmitting dtmf (bit 5 should be set to ?1?. bits 6 and 7 should be operated as described above). d3 d2 d1 d0 lower freq. (hz) (setting bit 4 = 0) upper freq. (hz) (setting bit 4 = 0) keypad symbol single tone freq. (hz) (setting bit 4 = 1) 0 0 0 0 941 1633 d 1633 0 0 0 1 697 1209 1 1209 0 0 1 0 697 1336 2 1336 0 0 1 1 697 1477 3 1477 0 1 0 0 770 1209 4 1209 0 1 0 1 770 1336 5 1336 0 1 1 0 770 1477 6 1477 0 1 1 1 852 1209 7 1209 1 0 0 0 852 1336 8 852 1 0 0 1 852 1477 9 852 1 0 1 0 941 1336 0 941 1 0 1 1 941 1209 * 941 1 1 0 0 941 1477 # 941 1 1 0 1 6 97 1633 a 697 1 1 1 0 770 1633 b 770 1 1 1 1 852 1633 c 852 the following table shows the settings required for transmitting modem progress tones. (set bit 4 to ?0? and bit 5 to ?0?. bits 6 and 7 should be operated as described earlier). d3 d2 d1 d 0 frequency (hz) tone description 0 0 0 0 550 guard 0 0 0 1 1300 calling 0 0 1 0 1800 guard 0 0 1 1 2100 answer 0 1 0 0 2225 answer
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 13 d/644a/6 gain blocks register ($e2) bits 0 to 3 (rg0 to rg3) control the levels of the receiver input gain block accordi ng to the following table: rg3 (bit 3) rg2 (bit 2) rg1 (bit 1) rg0 (bit 0) gain (db) 0 0 0 0 - 4.70 0 0 0 1 - 3.46 0 0 1 0 - 2.12 0 0 1 1 - 0.96 0 1 0 0 0.00 0 1 0 1 0.87 0 1 1 0 1.64 0 1 1 1 2.36 1 0 0 0 3.08 1 0 0 1 3.69 1 0 1 0 4.22 1 0 1 1 4.76 1 1 0 0 5.27 1 1 0 1 5.78 1 1 1 0 6.21 1 1 1 1 6.58 the gain should be set in a calibration procedure in order to trim out the effects of any component tolerances which may give rise to a variation in the carrier detect threshold levels. bits 4 to 7 (tg0 to tg3) control the levels of the transmit path gain block according to the following table: tg3 (bit 7) tg2 (bit 6) tg1 (bit 5) tg0 (bit 4) gain (db) 0 0 0 0 off (o/p at bias) 0 0 0 1 - 5.6 0 0 1 0 - 5.2 0 0 1 1 - 4. 8 0 1 0 0 - 4.4 0 1 0 1 - 4.0 0 1 1 0 - 3.6 0 1 1 1 - 3.2 1 0 0 0 - 2.8 1 0 0 1 - 2.4 1 0 1 0 - 2.0 1 0 1 1 - 1.6 1 1 0 0 - 1.2 1 1 0 1 - 0.8 1 1 1 0 - 0.4 1 1 1 1 0.0
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 14 d/644a/6 tx data byte register ($e3) the bytes of data to be transmitted should be loaded into this register. it is double buffered, thus giving the user up to 8 bit periods to load in the next 8 bits. each byte represents 4 lots of 2 consecutive bits (dibits) with the most significant dibit being loaded first (taking bit 7 of this re gister as being the most significant). the data is reversed so that it is transmitted least significant dibit first. these dibits represent a transmitted phase change according to the following table: dibit values phase change note that the left - hand di git of the dibit is 00 + 90 the one occurring first in the data stream 01 0 as it enters the modulator portion of the 11 + 270 modem after the scrambler. 10 + 180 uart mode register ($e4) (bit 7 and bit 6) reserved for future use. these bits should be set to ?0?. sync/async (bit 5) when this bit is ?0?, data will be transmitted and received in normal 8 bit mode without modification. when this bit is ?1?, data will be transmitted and received with one start bit (?0?) and 7/8 bits, odd /even parity, 0 or 1 or 2 stop bits according to the remainder of the bits in this register. prior to handshaking the uart mode register needs bit 5 cleared for synchronous operation. after the handshaking procedure has completed bit 5 the uart m ode register should be set for asynchronous data transfer. the remaining bits of this register should be configured to be compatible with the modem you are talking to. the minimum number of stop bits only applies to the transmitter, the receiver does not require any defined number of stop bits. stop bits a and b (bits 4 and 3) the minimum number of stop bits transmitted after each data byte plus parity is defined by the table below. stop bits a stop bits b number of stop bits 0 0 0 0 1 1 1 0 1 1 1 2 the receiver does not require any defined number of stop bits. parity enable (bit 2) when this bit is ?1? an extra bit is added after the data to indicate the parity of that data. when set to ?0?, parity is disabled. this bit affects both transmitter and receiver. parity odd/even (bit 1) when this bit is ?1? the parity is set odd, and when this bit is ?0? the parity is set even. this bit affects both transmitter and receiver. data bits 8/7 (bit 0) when this bit is ?1? the data is set to transmit and receive 7 bits i.e. bits 0 - 6. when this bit is ?0? the normal 8 bits of data is programmed. this bit affects both transmitter and receiver.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 15 d/644a/6 tx psk mode register ($e7) (bit 7) reserved for future use. this bit should be set to ?0?. txon enab (bit 6) this bit enables or powersaves the inverted output of the line driving amplifier (txon). when set to ?1? txon is enabled; together with txo these outputs provide sufficient complementary output to drive a line ev en at low vdd. when set to ?0? the txon output is powersaved, reducing the total supply current for applications in which a single - ended output is sufficient. scramb unlock (bit 5) when this bit is set to ?1? the scrambler will check for sequences o f 64 consecutive ones at its output (caused by scrambler lockup) and once detected it will invert the next input to the scrambler. when this bit is set to ?0? the lock - up prevention is disabled. scramb enable (bit 4) when this bit is set to ?1? the tx data is passed through the scrambler. when it is set to ?0? the scrambler is bypassed. equal et1 and et0 (bits 3 and 2) these 2 bits control the level of equalisation applied to the transmitted signal according to the following table: et1 (bi t 3) et0 (bit 2) transmitter equalisation 0 0 no equalisation 0 1 low 1 0 medium 1 1 high see figures 5a and 5b for the typical equaliser responses. the equaliser is automatically powersaved when both et1 and et0 are set to '0'. enable (bit 1) when this bit is set to ?1? the internal output of the psk modulator is enabled. when it is set to ?0? the internal output of the psk modulator is set to v bias . associated flags are only set when this bit is ?1?. hi/lo band (bit 0) this b it determines whether the transmitted psk signal should occupy the low channel (900hz - 1500hz) or the high channel (2100hz - 2700hz). when the bit is set to ?0? the low channel is selected. when it is set to ?1? the high channel is selected.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 16 d/644a/6 rx psk m ode register ($e8) (bit 7) reserved for future use. this bit should be set to ?0?. cpbw select (bit 6) when this bit is set to ?1? the call progress detector bandwidth is approximately 300hz - 620hz. when this bit is set to ?0? the call progress det ector bandwidth is approximately 400hz - 620hz. de - scramb unlock (bit 5) when this bit is set to ?1? the de - scrambler will check for sequences of 64 consecutive ones at its input and once detected it will invert the next output from the de - scrambler. when this bit is set to ?0? the all ones detection is disabled - it should be set as such until the handshaking sequence is complete. de - scramb enable (bit 4) when this bit is set to ?1? the rx data is passed through the de - scrambler. when it is s et to ?0? the de - scrambler is bypassed. equal er1 and er0 (bits 3 and 2) these 2 bits control the level of equalisation applied to the received signal according to the following table: er1 (bit 3) er0 (bit 2) receiver equalisation 0 0 no equal isation 0 1 low 1 0 medium 1 1 high see figures 5a and 5b for the typical equaliser responses. the equaliser is automatically powersaved when et1 and et0 are set to ?no equalisation? (?0?, ?0?). enable (bit 1) when this bit is set to ?1? t he psk receiver is enabled. when it is set to ?0? the receiver is disabled. associated flags are only set when this bit is ?1?. hi/lo band (bit 0) this bit determines whether the received psk signal should be filtered and derived from the low chann el (900hz - 1500hz) or the high channel (2100hz - 2700hz). when this bit is set to ?0? the low channel is selected. when it is set to ?1? the high channel is selected.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 17 d/644a/6 irq mask bits ($ee) this register is used to control the interrupts (irqs) as de scribed below: rx parity mask (bit 7) when this bit is set to ?1? it enables an interrupt that occurs when the rx parity flag (bit 7, flags register, $ef) changes from ?0? to ?1? i.e. there is an rx parity error. when this bit is ?0? the interrupt is ma sked. ring detect mask (bit 6) when this bit is set to ?1? it enables an interrupt that occurs when ring detect change flag (bit 6, flags register, $ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. detect mask (bit 5) when this bit is set to ?1? it enables an interrupt that occurs when detect flag (bit 5, flags register, $ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. rx data overflow mask (bit 4) when this bit is set to ?1? it enabl es an interrupt that occurs when rx data overflow flag (bit 4, flags register, $ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. rx data ready mask (bit 3) when this bit is set to ?1? it enables an interrupt that occurs when r x data ready flag (bit 3, flags register, $ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. tx data underflow mask (bit 2) when this bit is set to ?1? it enables an interrupt that occurs when tx data underflow flag (bit 2, flags register, $ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. tx data ready mask (bit 1) when this bit is set to ?1? it enables an interrupt that occurs when tx data ready flag (bit 1, flags register, $ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. unscram mark mask (bit 0) when this bit is set to ?1? it enables an interrupt that occurs when unscram mark flag (bit 0, flags register, $ef) changes from ?0? to ?1?. when this bit is ?0? the i nterrupt is masked.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 18 d/644a/6 read only ?c - bus? registers register name hex address/ command bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) rx data byte $ea d7 d6 d5 d4 d3 d2 d1 d0 tones detect $ec 1 ring detect call prgrss detect carrier detect answer detect 0 0 un - scram mark detect flags $ef rx parity ring detect change detect rx data over - flow rx data ready tx data under - flow tx data ready un - scram mark rx data byte register ($ea) th is register contains the last byte of data received. it is updated every 8 bits at the same time as the rx data ready flag is set. the rx data byte register is double buffered, thus giving the user up to 8 bit periods to read the data before it is overwr itten by the next byte. each received phase change is decoded into 2 bits (a dibit). the incoming dibits fill this register starting at the most significant end (bits 7 and 6). phase change dibit values note that the left - hand digit of the dibit will be the more + 90 00 significant of the 2 bits when located in this register. 0 01 + 270 11 + 180 10 tones detect register ($ec) this register provides information as to the presence or absence of various signalling conditions detected by the receiver. a logic ?1? indicates that the signalling condition is present; a logic ?0? indicates that it is absent. (bit 7) this bit will be set to ?1?. ring detect (bit 6) indicates the status of the ring/line polarity reversal detector circuit . the logic level of this bit represents the level of the internal ?ring detect? node (see figure 1 block diagram). call prgrss detect (bit 5) indicates the detection of call progress tones in the selected band. (300hz to 620hz or 400hz to 620hz). carrier detect (bit 4) indicates the detection of a carrier in the received channel. answer detect (bit 3) indicates the detection of an answer tone of 2100hz or 2225hz. (bits 2 and 1) these bits will be set to ?0?. unscram mark detect (bit 0) indicates the detection of unscrambled binary one in the received data for a period of time of 160ms. note that detect bits 5, 4 and 3 are mutually exclusive and are enabled by the setting of the detect det1 and det0 bits (set - up registers bits 5 and 4). all of the detect bits in the tones detect register - except for ring detect (bit 6) - require the rx psk mode register enable bit to be set to ?1?. flags register ($ef) the flags register is used to indicate when the device requires attention. when a flag becomes set to ?1? and its corresponding mask bit is ?1? then an interrupt (irqn) will be generated. immediately after the flags register has been read, all the bits will be reset to ?0? and consequently any interrupt will be cleared.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 19 d/644a/6 rx pa rity flag (bit 7) when this bit is ?1? the received parity is in error. when this bit is ?0? the received parity is correct. ring detect change flag (bit 6) when ring detect (tones detect register, bit 6) changes state, this bit will be set to ?1 ?. detect flag (bit 5) when any of the following bits - call prgrss detect, carrier detect or answer detect (tones detect register bits 5, 4, 3) - change state, this bit will be set to ?1?. rx data overflow flag (bit 4) if received data is n ot read out of the device within the 8 - bit window of rx data ready going high, then this bit will be set to ?1? to indicate an error condition. rx data ready flag (bit 3) when a full byte of data is received and is available in the rx data byte regi ster, this bit will be set to ?1?. there is then an 8 - bit window during which the rx data byte register must be read. tx data underflow flag (bit 2) if data is not loaded into the tx data byte register within the 8 - bit window of tx data ready going high, then this bit will be set to ?1? to indicate an error condition. tx data ready flag (bit 1) when the tx data buffer is ready to receive a new byte of data, this bit will be set to ?1?. there is then an 8 - bit window for the loading of the tx da ta byte register. unscram mark flag (bit 0) when the unscram mark detect bit (tones detect register bit 0) changes state, this bit will be set to ?1?.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 20 d/644a/6 0.0e+00 1.0e-04 2.0e-04 3.0e-04 4.0e-04 5.0e-04 6.0e-04 7.0e-04 8.0e-04 9.0e-04 1.0e-03 1.1e-03 1.2e-03 1.3e-03 1.4e-03 1.5e-03 1.6e-03 1.7e-03 1.8e-03 1.9e-03 2.0e-03 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 frequency (hz) group delay (secs) lowband low medium high figure 5a transmit/receive equaliser responses: lowband 0.0e+00 1.0e-04 2.0e-04 3.0e-04 4.0e-04 5.0e-04 6.0e-04 7.0e-04 8.0e-04 9.0e-04 1.0e-03 1.1e-03 1.2e-03 1.3e-03 1.4e-03 1.5e-03 1.6e-03 1.7e-03 1.8e-03 1.9e-03 2.0e-03 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 frequency (hz) group delay (secs) highband low medium high figure 5b transmit/receive eq ualiser responses: highband the CMX644A utilises two internal equalisers - one is configured for the high band, the other for the low band. the transmit and receive paths will be internally switched through the equaliser appropriate to their hi/lo band s ettings. in the event of both transmit and receive paths being set to the same band, both equalisers will be bypassed.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 21 d/644a/6 1.6 application notes 1.6.1 line interface a lin e interface circuit is needed to provide dc isolation between the modem and the line, to perform line impedance termination, and to set the correct transmit and receive signal levels. 4 - wire line interface figure 6a shows an interface circuit for use with a 600 w 4 - wire line. the line terminations are provided by r10 and r15, while r11 and r13 should be selected to give the desired transmit and receive levels. when v dd = 5.0v, the gain of the receive input amplifier (r12/r11) should be 6db (times 2.0) plus whatever additional gain is required to compensate for the loss of the input transformer. at other values of v dd the amplifier gain should be multiplied by the ratio v dd / 5.0. thus for r12 = 100k w : r11 = 100 k w * (5.0/v dd ) / (input transformer loss * 2.0) where the ?input transformer loss? = (rx level on 4 - wire line) / (level at point a of figure 6a). assuming a transformer loss of about 1db, r11 should be 47k w at v dd = 5.0v, and 68k w at 3.3v. the value of the resistor r11 is optimised for the carrier detect level. increasing the input gain (by reducing the value of r11) will improve modem sensitivity. note relay circuit, ac and dc loads a nd line protection are not shown for clarity. r10 600 w r14 100k w c10 100nf r11 see text r15 600 w c11 330pf r12 100k w c12 330pf r13 see text c13 100nf resi stors 1%, capacitors 20%. figure 6a 4 - wire line interface circuit
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 22 d/644a/6 in the transmit direction, the level on the 4 - wire line is determined by the level at the top pin, the gain of the output buffer amplifier, a loss of nominally 6db due to the line termination resistor r15, and the loss in the transformer. the top pin signal level is proportional to v dd and is also affected by the setting of the transmitter programmable gain block. assuming that the tx progr ammable gain block is set to - 2db (giving a psk signal level of - 4db wrt 775mvrms at the top pin when v dd = 5.0v) and that there is 1db loss in the transformer, then: tx psk 4 - wire line level = - (4 +6 +1) + 20 * log10(2 * r14/r13) + 20 * log10(v dd / 5 .0) dbm for example, to generate a nominal tx fsk line level of - 10dbm, r13 should be 180k w when v dd = 5.0v, falling to 120k w at 3.3v. 2 - wire line interface figure 6b shows an interface circuit suitable for c onnection to a 600 w 2 - wire line. the circuit also shows how a relay may be driven from the rlydrv pin. note that when the CMX644A is powered from less than 5.0v, buffer circuitry will be required to drive a 5v relay. note: ac and dc loads and line pr otection are not shown for clarity r11 see text r15 600 w c11 330pf r12 100k w r16 120k w c12 330pf r13 see text r17 100k w c13 10nf r14 100k w c14 100nf resistors 1%, capacitors 20% figure 6b 2 - wire line interface circuit this circuit includes a 2 - wire to 4 - wire hybrid circuit, formed by r11, r15, r16, r17, c13 and the impedance of the line itself, which ensures that the modem receive input and transmit output paths are both coupled efficiently to the line, while minimising coupling from the modem?s transmit signal into the receive input. the values of r11 and r13 should be calculated in the same way as for the 4 - wire interface circuit of figure 6a. note that the component values r17 and c13 depend on the transformer characteristics and should be adjusted to achieve a flat frequency response measured at the rxo pin.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 23 d/644a/6 1.6.2 ring detector inte rface figure 7 shows how the CMX644A may be used to detect the large amplitude ringing signal received at the start of an incoming telephone call. the ring signal is usually applied at the subscriber's exchange as an ac voltage inserted in series with one of the telephone wires and will pass through either c20 and r20 or c21 and r21 to appear at the top end of r22 (point x in figure 7) in a rectified and attenuated form. the signal at point x is furth er attenuated by the potential divider formed by r22 and r23 before being applied to the CMX644A rd input. if the amplitude of the signal appearing at rd is greater than the input threshold (vthi) of schmitt trigger 'a' then the n transistor connected to r t will be turned on, pulling the voltage at rt to v ss by discharging the external capacitor c22. the output of the schmitt trigger 'b' will then go high, setting bit 6 (ring detect) of the tones detect register. the minimum amplitude ringing signal that i s certain to be detected is ( 0.7 + vthi * [r20 + r22 + r23] / r23 ) * 0.707 vrms where vthi is the high - going threshold voltage of the schmitt trigger a with r20 - 22 all 470k w as figure 7, then setting r23 to 68k w will guarantee detection of ringing signals of 40vrms and above for v dd over the range 3.0 to 5.5v. r20,21,22 470k w c20,21 0.1 m f r23 see text c22 0.33 m f r24 470k w d1 - 4 1n4004 resistors 1%, capacitors 20% figure 7 ring signal detector interface circuit
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 24 d/644a/6 if the time constant of r24 and c22 is large enough then the voltage on rt will remain below the threshold of the 'b' schmitt trigger for the duration of a ring cycle. the time for the voltage on rt to charge from v ss towards v dd can be derived from the formula v rt = v dd * [1 - exp( - t/(r24 x c22)) ] as the schmitt trigger high - going input threshold voltage (vthi) has a minimum value of 0 .56 x v dd , then the schmitt trigger b output will remain high for a time of at least 0.821 x r24 x c22 following a pulse at rd. the values of r24 and c22 given in figure 7 (470k w and 0.33 m f) give a minimum rt charge time of 100 msec, which is adequate for ring frequencies of 10hz or above. note that the circuit will also respond to a telephone line voltage reversal. if necessary the m c can distinguish between a ring signal and a line voltage reversal by me asuring the time that bit 6 of the tones detect register (ring detect) is high. 1.6.3 software protocol for transmitting psk data bytes in order to transmit psk data, the follow ing steps should be followed. for clarity, not all bit settings are described here (but hi/lo band, equalisation, guard tones, number of stop bits etc. should be set as appropriate). 1. program setup register for correct crystal frequency. wait at least 20ms if device was previously in ?zero power? mode before proceeding. 2. set tx gain block (gain blocks register $e2) to required gain. set uart mode. 3. load first data byte into tx data byte register ($e3). 4. read flags register ($ef) in order to c lear it. 5. set irq mask bits register ($ee bits 2 and 1) to allow appropriate interrupts (tx data underflow and tx data ready). note: if an underflow occurs, continuous mark (?1?) will be transmitted. 6. set enable bit (tx psk mode register $e7) to ?1 ?. the first byte of data will now be transmitted by the device. 7. wait for a tx data ready generated interrupt (read flags to check and clear the irq). 8. load next tx data byte. 9. go to 7. note that the transmission should be terminated by settin g the enable bit (tx psk mode register) to ?0?.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 25 d/644a/6 1.6.4 software protocol for receiving psk data bytes 1. with the device out of ?zero power? mode, set up all receiver - related function s: gain, hi/lo band, equalisation, uart mode, etc. 2. perform a dummy read of the rx data byte register ($ea) and discard the result. 3. read flags register ($ef) in order to clear it. 4. set irq mask bits register ($ee bits 7, 4 and 3) to allow appropriate i nterrupts (rx parity, rx data overflow and rx data ready). 5. set enable bit (rx psk mode register $e8) to ?1?. 6. wait for an rx data ready generated interrupt (read flags to check and clear the irq). 7. read rx data byte ($ea). 8. go to 5. 1.6.5 h andling underflow and overflow conditions if the rx data byte register has not been read before the next byte of rx data is received, then the rx data overflow flag will be set and the rx data byte register will hold the most recent byte of received data. the rx data ready flag will remain set if the flags register is not read before the overflow condition occurrs. both rx data ready and rx data overflow flags are reset upon reading th e flags register, and are not set again until after the rx data byte register has been read (ie the overflow condition has been cleared). if the tx data byte register is not written to before the last byte of tx data is sent, then the tx data underflow fl ag will be set and the tx data will then consist of continuous mark ("1"), which will normally be scrambled, until new data is loaded into the tx data byte register. the tx data ready flag will remain set if the flags register is not read before the under flow condition occurrs. both tx data ready and tx data underflow flags are reset upon reading the flags register, and are not set again until after the tx data byte register has been loaded with new data (ie the underflow condition has been cleared). c - b us transactions to handle underflow and overflow conditions are shown in the timing daigram of figure 8. note that allowance should be made for c - bus latency (t del and t load ) when changing register settings. eg to change the number of tx stop bits transm itted with all subsequent data (stop bits a and b), first wait until the tx data ready flag is set. if this check is not made, then the number of stop bits in the tx data byte which is currently being sent will be changed.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 26 d/644a/6 figure 8 async mode (rx and tx)
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 27 d/644a/6 1.7 performance specification 1.7.1 electrical performance 1.7.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (v dd - v ss ) - 0.3 7.0 v voltage on any pin to v ss - 0.3 v dd + 0.3 v current into or out of v dd and v ss pins - 50 +50 ma current sink into rlydrv pin 0 +50 ma current into or out of any other pin - 20 +20 ma d2 package min. max. units total allowable power dissipation at tamb = 25c - 800 mw ... derating - 13 mw/c storage temperature - 55 +125 c operating temperature - 40 +85 c d5 package min. max. units total allowable power dissip ation at tamb = 25c - 550 mw ... derating - 9 mw/c storage temperature - 55 +125 c operating temperature - 40 +85 c p4 package min. max. units total allowable power dissipation at tamb = 25c - 800 mw ... derating - 13 mw/c st orage temperature - 55 +125 c operating temperature - 40 +85 c 1.7.1.2 operating limits correct operation of the device outside these limits is not implied. nominal xtal frequencies are 3.6864mhz, 7.372800mhz, 11.0592mhz. min max. units suppl y (v dd - v ss ) 2.7 5.5 v operating temperature - 40 +85 c xtal frequency - 100 +100 ppm
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 28 d/644a/6 1.7.1.3 operating characteristics for the following conditions unless otherwise specified: v dd = 2.7v at tamb = 25c and v dd = 3.0v to 5.5v at tamb = - 40 to +85c. 0dbm corresponds to 775mvrms. notes min. typ. max. units dc parameters i dd (?zero power?) 2 - 1 - m a i dd (operating at v dd = 3.0v and tamb = 25c) 2 - 3.2 4.0 ma i dd (as above, but with equalisation enabled) 2 - - 4.6 m a logic ?1? input level 5 70% - - v dd logic ?0? input level 5 - - 30% v dd logic input leakage current (vin = 0 to v dd ), (excluding xtal/clock input) - 1.0 - +1.0 a output logic ?1? level (i oh = 360a) v dd - 0.4 - - v output logic ?0? level (i ol = 360a) - - 0.4 v irqn o/p ?off? state current (vout = v dd ) - - 1.0 a schmitt trigger input high - going threshold (vthi) (see figure 8) 0.56v dd - 0.56v dd +0.6v v schmitt trigger input low - going thr eshold (vtlo) (see figure 8) 0.44v dd - 0.6v - 0.44v dd v relay driver pull - down on resistance (v dd = 5.0v, 50ma maximum load current) - 37.0 - w xtal/clock input pulse width (?high? or ?low?) 3 40 - - ns input impedance (at 100hz) 10 - - m w gain (i/p = 1mv rms at 1khz) 20 - - db ac parameters transmitter (at top pin) guard tones level (below psk) of 550hz - - 3.0 - db level (below psk) o f 1800hz - - 6.0 - db frequency accuracy - 0.25 - +0.25 % psk output transmitted level 1, 4,8 - 3.0 - 2.0 - 1.0 dbm distortion - 2.0 5.0 % dtmf output transmitted level: high group 1, 4 - 2.0 - 1.0 0 dbm twist (high group - low group levels) 4 - 2.0 - db distortion 2.0 5 % frequency accuracy - 0.25 - +0.25 %
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 29 d/644a/6 notes min. typ. max. units receiver dynamic range (v dd = 5.0v) - 45 - db carrier detect t hreshold: will decode 1, 6 - - - 43 dbm threshold: will not decode 1, 6 - 48 - - dbm hysteresis 7 - 2.0 - db response time (delay) - 20 50 ms de - response time (hold) - 20 50 ms answer tone detector threshold : will decode 1, 6 - - - 43 dbm threshold: will not decode 1, 6 - 48 - - dbm response time (delay) - 20 50 ms de - response time (hold) - 20 50 ms decode bandwidth (must decode) 2.0 - - % decode bandwidth (must not decode) - - 6. 0 % call progress detector effective bandwidth 9 300/400 - 620 hz threshold: will decode 1, 6 - - - 43 dbm threshold: will not decode 1, 6 - 48 - - dbm response time (delay) - 20 50 ms de - response time (hold) - 20 50 ms programmable gain blocks rx gain block nominal range - 4.70 - +6.58 db (step size: see register description) step accuracy - 0.5 - +0.5 db tx gain block nominal range - 5.6 - 0.0 db step size - 0.4 - db step accuracy - 0.2 - +0.2 db notes: 1. at v dd = 5.0v only. signal levels or currents are proportional to v dd . 2. not including any current drawn from the modem pins by external circuitry. 3. timing for an external input to the clock/xtal pin. 4. tx gain block set to 0db and measured with a pure tone or dtmf tone pair, without equalisation. 5. excluding rd, rt and xtal/clock pins. 6. rx gain block nominally set to 0db but adjusted if necessary for component tolerances . measurement point for threshold levels is prior to receive input amplifier circuit (point a on figure 6a), with external components setting gain to 9db. detector levels measured with a pure tone. 7. hysteresis may be increased, if required, by adding one step (increasing the gain of) to the rx gain block when a signal is detected and by removing this step when the signal is no longer detected. 8. measured with a 511 - bit pseudorandom sequence. 9. depending on the setting of the cpbw select bit in the rx psk mode register. 10. measured without equalisation.
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 30 d/644a/6 0 0.5 1 1.5 2 2.5 3 3.5 2.5 3 3.5 4 4.5 5 5.5 vdd vin vthi vtlo figure 9 typical schmitt trigger input voltage vs. v dd tx timings (see figure 4a) notes min. typ. max. units tx delay from tx data loaded (tdel) 10 0 - 0.833 ms tx output t o tx reload signal (tload) 10 0 - 8.33 ms tx parity to tx underflow flag set (tufl) 10 0 - 1.667 ms rx timings (see figure 4b) notes min. typ. max. units parity to rx data ready flag set (trdy) 10 - 1.667 - ms
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 31 d/644a/6 1.7 .1.3 operating characteristics (continued) ?c - bus? timings (see figure 10) notes min. typ. max. units t cse csn - enable to clock - high time 100 - ns t csh last clock - high to csn - high time 100 - ns t loz clock - low to reply output enable time 0 - ns t hiz csn - high to reply output 3 - state time - 1.0 s t csoff csn - high time between transactions 1.0 - s t nxt inter - byte time 200 - ns t ck clock - cycle time 200 - ns t ch serial clock - high time 100 - ns t cl serial clock - low tim e 100 - ns t cds command data set - up time 75 - ns t cdh command data hold time 25 - ns t rds reply data set - up time 75 - ns t rdh reply data hold time 0 - ns note: these timings are for the latest version of the ?c - bus? as embodied in t he CMX644A, and allow faster transfers than the original ?c - bus? timings given in cml publication d/800/sys/3 july 1994. figure 10 ?c - bus? timing
v22 and bell 212a modem CMX644A ? 2000 consumer microcircuits limited 32 d/644a/6 1.7.2 packaging figure 11a 24 - pin soic (d2) mechanical outli ne: order as part no. CMX644Ad2 figure 11b 24 - pin ssop (d5) mechanical outline: order as part no. CMX644Ad5
v22 and bell 212a modem CMX644A handling precautions: this product includes input protection, however, precautions should be taken to prevent device damage from electro - static discharge. cml does not assume any responsibility for the use of any circuitry d escribed. no ipr or circuit patent licences are implied. cml reserves the right at any time without notice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circuit parameters is not necessarily performed. oval park - langford maldon - essex cm9 6wg - england telephone: +44 (0)1621 875500 telefax: +44 (0)1621 875600 e - mail : sales@cmlmicro.co.uk http://www.cmlmicro.co.uk figure 11c 24 - pin dil (p4) mechanical outline: order as part no. CMX644Ap4

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